Receiving apparatus and receiving method

ABSTRACT

An LPF eliminates noise components from baseband signal obtained by performing a frequency conversion on the received signal on the basis of the received wireless transmission wave. A passband setting part sets the upper limit of frequency of passband in the LPF at a high frequency while a synchronization signal is not detected and at a low frequency after a synchronization signal is detected.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a receiving apparatus, in particular toa receiving apparatus for receiving and demodulating a wirelesstransmission wave, and to a receiving method for receiving the wirelesstransmission wave.

2. Description of the Related Art

A receiving apparatus has been proposed which employs a so-called FSK(Frequency Shift Keying) scheme as a digital modulation scheme used in aspecified low power radio systems (For example, Japanese patentapplication Laid-Open No. H09-162936). Such receiving apparatus includesa mixer, a local oscillator, a filter such as a low-pass filter(referred to as “LPF” in the following description) and a demodulator.The mixer generates an intermediate frequency signal by mixing areceived signal received by an antenna and a local oscillation signalgenerated in the local oscillator. The LPF eliminates noise componentsfrom the intermediate frequency signal. The demodulator demodulatesinformation data such as audio, video and text on the basis of desiredfrequency components in the intermediate frequency signal from which thenoise components are eliminated by the LPF.

In mobile communications, the receiving apparatus deals with a carriersignal which has relatively high frequency. Therefore, the localoscillator is desired to generate the local oscillation signal with highfrequency and high stability. However, certain amount of frequencydeviations occur in the local oscillation signal, even if the localoscillator with high stability is used. The amount of the frequencydeviations become larger when using a relatively inexpensive oscillator,for example a crystal oscillator. The frequency deviations also occur inthe intermediate frequency signal.

Therefore, the receiving apparatus includes a frequency offsetcorrection means which detects the frequency deviations occurring in theintermediate frequency signal from which the noise components areeliminated by the LPF and corrects the frequency offset corresponding tothe detected frequency deviation.

SUMMARY OF THE INVENTION

The LPF might eliminate signal components in the desired band to bereceived, when relatively large frequency offset occurs. At this time,the frequency offset cannot be detected in a frequency detector providedin the latter part of the LPF. However, if the passband of the LPF isbroadened, the amount of noises which pass through the LPF increases.For this reason, there occurs a problem that the reception sensitivityis reduced.

It is an object of the present invention to provide a receivingapparatus and a receiving method capable of good reception in which thefrequency offset is eliminated without declining of receptionsensitivity.

The receiving apparatus for demodulating a received signal obtained byreceiving a wireless transmission wave which is modulated according to aseries of data sequences including frames each having a synchronizationsignal, the receiving apparatus comprising:

a frequency converting part for performing a frequency conversion on thereceived signal and obtaining a frequency converted signal including abaseband signal,

a filter for eliminating high frequency noise components from thefrequency converted signal and obtaining a high frequency noiseeliminated signal,

a frequency detector for performing a frequency detection on the highfrequency noise eliminated signal and obtaining a frequency detectionsignal,

a frequency offset detector for detecting a frequency offset occurringin the frequency converted signal on the basis of the frequencydetection signal,

a frequency correction part for sifting frequency of the frequencyconverted signal by the amount of the frequency offset,

a synchronization detector for detecting the presence of thesynchronization signal in each of said frames, and generating asynchronization detection signal which has a first level as far as thesynchronization signal is not detected and has a second level when andafter the synchronization signal is detected; and

a passband setting part for setting an upper limit of frequency of apassband in the filter at a lower frequency within a time period inwhich the synchronization detection signal is kept at the second levelthan that within a time period in which the synchronization detectionsignal is kept at the first level.

A receiving method according to the present invention is a receivingmethod for a receiving apparatus comprising a frequency converting partfor performing a frequency conversion on the received signal andobtaining a frequency converted signal including a baseband signal, afilter for eliminating high frequency noise components from thefrequency converted signal and obtaining a high frequency noiseeliminated signal, a frequency detector for performing a frequencydetection on the high frequency noise eliminated signal and obtaining afrequency detection signal, and a frequency offset detector fordetecting a frequency offset occurring in the frequency converted signalon the basis of the frequency detection signal, the receiving methodcomprising the steps of:

detecting the presence of the synchronization signal in each frame, andgenerating a synchronization detection signal which has a first level asfar as the synchronization signal is not detected and has a second levelwhen and after the synchronization signal is detected,

setting an upper limit of frequency of a passband in the filter at lowerfrequency within a time period in which the synchronization detectionsignal is kept at the second level than that within a time period inwhich the synchronization detection signal is kept at the first level.

In the present invention, the LPF eliminates the noise components fromthe frequency converted signal obtained by performing a frequencyconversion on received signal which is the result of receiving wirelesstransmission wave. The passband width of the LPF is set at broadband,i.e. the upper limit of frequency is high, during a period in which thesynchronization signal is not detected. The passband width of the LPF isset at narrowband, i.e. the upper limit of frequency is low, after thesynchronization signal is detected.

Since the passband width of the LPF is broadened until thesynchronization signal is detected, the frequency offset is noteliminated in the LPF even if a large frequency offset occurs.Therefore, the frequency offset detector provided in the latter part ofthe LPF can detect the frequency offset and can perform a frequencycorrection on the basis of the detected frequency offset. On the otherhand, after the synchronization signal is detected, it is possible toeliminate noises superimposed on the frequency converted signalincluding a baseband signal because the passband width of the LPF isnarrowed. Therefore, it is possible to demodulate user data in a highreception sensitivity.

According to the present invention, it is possible to receive signalswhile eliminating the frequency offset without declining receptionsensitivity.

BRIEF DESCRIPTION OF THE DRAWINGS

Some aspects and other features of the present invention are explainedin the following description, taken in connection with the accompanyingdrawing figures wherein:

FIG. 1 is a block diagram showing a configuration of a receivingapparatus 100;

FIG. 2 is a graph showing a frequency characteristic L1 and a frequencycharacteristic L2 in a LPF 15;

FIGS. 3A-3E are time charts respectively showing wave variations ofsignals appearing in the receiving apparatus 100;

FIG. 4 is a graph showing in comparison reception characteristic J1 whenreproducing user data and reception characteristic J2 when reproducing apreamble;

FIG. 5 is a block diagram showing an example of the inner configurationof the LPF;

FIG. 6 is a block diagram showing an example of the inner configurationof a passband setting part 30; and

FIGS. 7A-7H are time charts respectively showing wave variations ofsignals appearing in the passband setting part 30.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a block diagram showing an entire configuration of a receivingapparatus 100 according to the present invention.

An antenna 10 receives a wireless transmission wave which is transmittedfrom a transmission apparatus (not shown). The antenna 10 supplies anamplifier which may be a low noise amplifier with a high frequencysignal RF on the basis of the wireless transmission wave as illustratedin FIG. 1. The wireless transmission wave is modulated in frequency inaccordance with data sequences. Each frame of the data sequencescomprises a preamble part consisting of a specific bit patternrepresenting a synchronization signal, a synchronization wordrepresenting a leading position of a user data piece, the user datapieces representing such information as audio, video and text. A digitalmodulation such as FSK is used as a modulation scheme in the modulation.

An amplifier 11 supplies a mixer 12 with a received signal AR obtainedby amplifying the high frequency signal RF.

The mixer 12 converts the received signal AR into an intermediatefrequency signal IFI which is corresponding to I-phase components in anintermediate frequency band by mixing a local oscillation signal fI inthe received signal AR. The mixer 12 further converts the receivedsignal AR into an intermediate frequency signal IFQ which iscorresponding to Q-phase components in the intermediate frequency bandby mixing a local oscillation signal fQ whose phase is shifted 90degrees with respect to the local oscillation signal FI in the receivedsignal AR. The mixer 12 supplies an A/D converter 13 with theseintermediate frequency signals IFI and IFQ.

The A/D converter 13 supplies a mixer 14 with an intermediate frequencydata signal IDI obtained by converting the intermediate frequency signalIFI and an intermediate frequency data signal IDQ obtained by convertingthe intermediate frequency signal IFQ.

The mixer 14 performs a frequency conversion on the intermediatefrequency data signal IDI into a baseband BB centering on the frequency0 [Hz] and generates a frequency converted signal including a basebandsignal BDI. The mixer 14 then supplies a LPF 15 with the frequencyconverted signal as illustrated in FIG. 2. The mixer 14 further performsthe frequency conversion on the intermediate frequency data signal IDQinto the baseband BB centering on the frequency 0 [Hz] and generates afrequency converted signal including a baseband signal BDQ. The mixer 14then supplies the LPF 15 with the frequency converted signal.

The LPF 15 is a filter that passes only signal components in apredetermined passband. The LPF 15 is explained as a low-pass filter inthe following description. The LPF 15 passes only low frequencycomponents in each of the frequency converted signals including thebaseband signals BDI and BDQ, the frequency of which are equal to orless than a frequency range including the baseband BB which isillustrated in FIG. 2. As a result, the LPF 15 supplies a frequencydetector 16 with high frequency noise eliminated signals BNI and BNQ.The high frequency noise eliminated signals BNI and BNQ are obtained byeliminating noise components having higher frequency than the frequencyrange.

The LPF 15 is the low-pass filter in which a cutoff frequency can bechanged, that is, in which the passband width can be changed on thebasis of a passband setting signal TS. The LPF 15 is set to a frequencycharacteristic having a passband width indicated by the passband settingsignal TS. The LPF 15 passes the low components in each of the frequencyconverted signals including the baseband signals BDI and BDQ accordingto the frequency characteristic. Therefore, when the passband settingsignal TS is a narrowband signal, the LPF 15 passes low frequencycomponents in each of the frequency converted signals including thebaseband signals BDI and BDQ, for example, according to a frequencycharacteristic L1 which is illustrated in FIG. 2. In addition, when thepassband setting signal TS is a broadband signal, the LPF 15 passes lowfrequency components in each of the frequency converted signalsincluding the baseband signals BDI and BDQ according to a frequencycharacteristic L2 in which the passband is broader in a high frequencyside than that in the frequency characteristic L1, as illustrated inFIG. 2.

The frequency detector 16 supplies a frequency offset detector 17 and afrequency offset eliminating part 18 with a frequency detection signalFD obtained by converting changes of frequency into changes of amplitudein the high frequency noise eliminated signals BNI and BNQ.

The frequency offset detector 17 detects a frequency offset occurs inthe frequency converted signals including the baseband signals (BDI,BDQ) and the intermediate frequency signals (IFI, IFQ) on the basis ofthe frequency detection signal FD. The frequency offset detector 17supplies the frequency offset eliminating part 18 and a frequencycontrol part 19 with an offset correction signal OC having a levelcorresponding to an amount of the detected frequency offset. Thefrequency offset represents deviations of the frequency of theintermediate frequency signal (IFI, IFQ) with respect to the referencefrequency.

The frequency offset detector 17 initializes the level of the frequencyoffset correction signal OC to zero at a timing of a leading edge of thefrequency control start signal ST indicating the initiation of thefrequency control.

The frequency offset eliminating part 18 eliminates the frequency offsetoccurring in the frequency detection signal FD on the basis of theoffset correction signal OC. The frequency offset eliminating part 18sifts a level of the frequency detection signal FD by the amount of thefrequency offset indicated by the offset correction signal OC. As aresult, the frequency offset eliminating part 18 generates a frequencydetection signal FDC by eliminating the frequency offset which isoccurring in the frequency detection signal FD. The frequency offseteliminating part 18 supplies a data reproducing part 20 with thefrequency detection signal FDC.

The data reproducing part 20 detects an appropriate symbol timing on thebasis of the frequency detection signal FDC. The data reproducing part20 demodulates the frequency detection signal FDC at the symbol timing.As a result, The data reproducing part 20 reproduces, at each frame, apreamble PA which includes a specific bit pattern representing asynchronization signal, a synchronization word CW which represents aleading (starting) point of a user data UD, and received data whichincludes the user data UD as illustrated in FIG. 3A.

The data reproducing part 20 detects the leading (starting) point of theuser data UD by detecting the synchronization word CW from the frequencydetection signal FDC. The data reproducing part 20 performs apredetermined demodulation processing and the error correctionprocessing in order on the frequency detection signal FDC from theleading point. By performing these processes, the data reproducing part20 reproduces information data such as audio, video and text representedby the user data UD. The data reproducing part 20 outputs theinformation data as a received information data.

The data reproducing part 20 reproduces a data bit sequence which iscorresponding to the preamble PA illustrated in FIG. 3A by thedemodulation processing on the frequency detection signal FDC. The datareproducing part 20 supplies a synchronization detector 21 with apreamble data PD which indicates the data bit sequence.

The synchronization detector 21 detects the specific bit pattern whichis corresponding to the synchronization signal from the leading point tothe tail point of the preamble data PD. The synchronization detector 21generates a synchronization signal CY which is kept at logic level 0during a period in which the specific bit pattern is not detected, andwhich is kept at logic level 1 during a period after which the specificbit pattern is detected.

In other words, the synchronization detector 21 generates thesynchronization signal CY which is kept at logic level 0 during a periodin which the synchronization signal included in the preamble PAillustrated in FIG. 3A and which makes transition from logic level 0 tolevel 1 when the synchronization signal is detected.

The synchronization detector 21 supplies the frequency control part 19and a passband setting part 30 with the synchronization detection signalCY.

The frequency control part 19 supplies the frequency offset detector 17and a frequency correction part 22 with the frequency control startsignal ST which represents a time point of transition of thesynchronization detection signal from logic level 0 to logic level 1,i.e. a time point of synchronization detection as illustrated in FIG.3C.

The frequency control part 19 converts an offset amount which isrepresented by the offset correction signal OC into a frequencycorrection amount for the local oscillation signal (fI, fW). Thefrequency control part 19 supplies the frequency correction part 22 witha frequency correction signal FC which has a level corresponding to thefrequency correction amount.

A frequency setting resistor 23 stores a reference frequency data FQwhich indicates a reference frequency of the local oscillation signal.The frequency setting resistor 23 supplies the frequency correction part22 with the reference frequency data FQ.

The frequency correction part 22 supplies a PLL (phase locked loop)circuit 24 with the frequency setting signal FST which indicates thereference frequency represented by the reference data FQ during a periodin which the frequency control start signal ST is kept at logic level 0as illustrated in FIG. 3C, i.e. a period in which the synchronizationsignal is not detected.

The frequency correction part 22 supplies the PLL circuit 24 with thefrequency setting signal FST which indicates the correction frequencywhich is obtained by adding the frequency correction amount indicated bythe frequency correction signal FC to the reference frequency indicatedby the reference frequency data FQ, or by subtracting the frequencycorrection amount from the reference frequency, during a period in whichthe frequency control start signal ST is kept at logic level 1 asillustrated in FIG. 3C.

The PLL circuit 24 includes a phase detector, a loop filter, a voltagecontrol oscillator, a divider and so on. The PLL circuit 24 generatesthe local oscillation signals fI and fQ having frequency represented bythe frequency setting signal FST. The PLL circuit 24 supplies the mixer12 with the local oscillation signals fI and fQ.

The passband setting part 30 supplies the LPF 15 with the passbandsetting signal TS which indicates broadband as first bandwidth during aperiod in which the synchronization detection signal CY is kept at logiclevel 0, i.e. a period in which the synchronization signal is notdetected. The passband setting part 30 supplies the LPF 15 with thepassband setting signal TS which indicates narrowband as secondbandwidth during a period in which the synchronization detection signalCY is kept at logic level 1, i.e. a period after which thesynchronization signal is detected.

It is described below with reference to a time chart which isillustrated in FIGS. 3A-3E, the operations of the receiving apparatus100 having the above configuration. FIGS. 3A-3E shows examples of wavevariations of signals appearing in operations of the receiving apparatus100 when frequency gap occurs between the intermediate frequency signalIFI and IFQ at the leading point of the frame of the received data, incase that the reference frequency of the local oscillation signals fIand fQ are at 920 Hz.

Since the frequency control is not yet started in the leading point ofeach frame of the received data, the frequency of the local oscillationsignals fI and fQ are set at 920 MHz which is the reference frequency.The frequency detection signal FD on which the frequency offset +50 kHzis superimposed can be obtained during a period which is correspondingto the preamble PA at the leading point of the frame, as illustrated inFIG. 3B. During this period, the frequency offset detector 17 suppliesthe frequency offset eliminating part 18 and the frequency offsetcontrol part 19 with the offset correction signal OC which indicates thefrequency offset +50 kHz as illustrated in FIG. 3D. The frequency offseteliminating part 18 generates the frequency detection signal FDC fromwhich the frequency offset is eliminated by shifting a level of thefrequency detection signal FD lower by the amount corresponding to thefrequency offset +50 kHz indicated by the offset correction signal OC.

According to such operations of the frequency offset elimination part18, the frequency detection signal FDC which is centered on zero levelis generated, before the frequency offset control part 19 startsfrequency control processing. The operations of the frequency offsetelimination part 18 makes it possible for the data reproducing part 20to reproduce data while suppressing bit errors. The synchronizationdetection signal CY makes transition from logic level 0 to level 1 asillustrated in FIG. 3C when the synchronization signal represented bythe specific bit pattern which is included in the preamble PA isdetected. So as to follow the synchronization detection signal CY, thefrequency control start signal ST makes transition from logic level 0 tologic level 1 as illustrated in FIG. 3C.

In response to the frequency control start signal ST at logic level 0,the frequency control part 19 takes in the offset correction signal OC.The frequency control part 19 supplies the frequency correction part 22with the frequency correction signal FC which indicates the amount ofthe frequency correction corresponding to the amount of the offsetcorrection (50 kHz) indicated by the offset correction signal OC. Thefrequency correction 22 supplies the PLL circuit 24 with the frequencysetting signal FST which indicates a correction frequency (919.950 MHz)obtained by subtracting the amount of frequency correction indicated bythe frequency correction signal FC from the reference frequency (920MHz) indicated by the reference frequency data FQ. The frequency of thelocal oscillation signal fI and fQ generated by the PLL circuit 24shifts from the initiation value 920 MHz to 919.950 MHz. As a result,the frequency gap between the intermediate frequency signal IFI and IFQis eliminated. The frequency offset in the frequency detection signal FDgradually shifts to zero as illustrated in FIG. 3E.

The frequency offset detector 17 initializes a level of the offsetcorrection signal OC to zero in response to the frequency control startsignal ST which is at logic level 1. Since the frequency gap iseliminated by the frequency correction to the local oscillation signal,it is not required for the frequency offset eliminating part 18 toperform an offset eliminating process. The receiving apparatus 100initializes the level of the offset correction signal OC to zero at astart timing of the frequency control in response to the frequencycontrol start signal ST which is at logic level 1.

The passband setting part 30 supplies the LPF 15 with the passbandsetting signal TS representing the broadband during a period in whichthe synchronization signal CY is kept at logic level 0, i.e. a period inwhich the synchronization signal is not detected. The LPF 15 passes lowfrequency components in each of the frequency converted signalsincluding the baseband signals BDI and BDQ with the frequencycharacteristic L2 which is broader than the frequency characteristic L1.Since the passband width of the LPF 15 is broadened, the frequencyoffset is not eliminated by the LPF 15 at the stage before thesynchronization signal is detected in each frame, even if a largefrequency offset occurs in the intermediate frequency signals IFI andIFQ. Therefore, the frequency offset detector 17 can detect relativelylarge offset such as described above. As a result, the frequency offsetcan be eliminated absolutely.

On the other hand, the passband setting part 30 supplies the LPF 15 withthe passband setting signal TS indicating the narrowband when thesynchronization detection signal CY is kept at logic level 1,i.e. afterthe synchronization signal is detected. As a result, the LPF 15 passeslow frequency components in the frequency converted signal including thebaseband signals BDI and BDQ with the frequency characteristic L1 whichis narrower than the frequency characteristic L2, i.e. an upper limit offrequency of which is lower than that of the frequency characteristic L2as illustrated in FIG. 2. In other words, the passband setting part 30makes it possible for the LPF 15 to eliminate the noise superimposed onthe intermediate frequency signals (IFI, IFQ) and the frequencyconverted signals including the baseband signals (BDI, BDQ) by makingthe passband width of the LPF 15 narrow after the synchronization signalis detected in each frame. As a result, it is possible to demodulate theuser data UD with high reception sensitivity.

The reception sensitivity of the receiving apparatus 100 declines whenthe passband of the LPF 15 is the broadband, compared to when thepassband of the LPF 15 is the narrowband. However, the specific bitpattern which represents the synchronization signal in the preamble PAis a pattern known in the receiving apparatus. Therefore, it is possibleto determine bit series obtained by reproducing the preamble PA as thespecific bit pattern, even if errors are mixed to the bit series. Thereception characteristic J2 for a synchronization detection (preambledetection) which is necessary when reproducing the preamble PA isbroader than the reception characteristic J1 which is necessary whenreproducing the user data UD, as illustrated in FIG. 4. Therefore, it ispossible to detect the synchronization signal without declining ofreception sensitivity even if the bandwidth of the LPF 15 is broad.

The receiving apparatus 100 which is illustrated in FIG. 1 can receivesignals while eliminating the frequency offset without declining ofreception sensitivity.

A digital filter can be adopted to the LPF 15. In that case, thepassband width can be changed by changing the frequency of the clocksignal which is supplied to the digital filter.

FIG. 5 is a circuit diagram of the LPF 15 when it comprises adigital-type transversal filter. FIG. 6 is a circuit diagram showing anexample of the internal constitution of the passband setting part 30when the digital-type transversal filter illustrated in FIG. 5 isadopted to the LPF 15.

The transversal filter which is illustrated in FIG. 5 includes n (n isan integer of 2 or more) flip flops FF1˜FFn connected in cascade, ncoefficient multipliers M1˜Mn and an adder AD. The flip flops FF1˜FFntake in the frequency converted signal including the baseband signal BDI(BDQ) which is supplied from the mixer 14, while sequentially sifting ata timing of a leading edge of the passband setting signal TS. Thecoefficient multipliers M1˜Mn multiplies each of output signals from theflip flops FF1˜FFn by filter coefficients C1˜Cn. The adder AD obtains anaddition result by adding multiplication results in the coefficientmultipliers M1˜Mn. The adder AD outputs the addition result as the abovehigh frequency noise eliminated signal BNI (BNQ).

The passband setting part 30 includes a resistor 301, 302, a selector303, a counter 304, a comparator 305 and an AND gate 306.

The resistor 301 stores, in advance, fixed count value A for setting ahigh frequency clock. The resistor 301 supplies the comparator 305 withthe fixed count value A. The resistor 302 stores, in advance, fixedcount value B for setting a high frequency clock which is larger thanthe fixed count value A. The resistor 302 supplies he selector 303 withthe fixed count value B.

The selector 303 selects one of the fixed count values A and B on thebasis of the synchronization detection signal CY. The selector 303supplies the comparator 305 with the selected one as the division valueDV. The selector 303 selects the fixed count value A when thesynchronization detection signal CY indicates logic level 0 asillustrated in FIG. 3C. The selector then supplies the comparator 305with the fixed count value A as the division value DV. The selectorselects the fixed count value B when the synchronization detectionsignal CY indicates logic level 1. The selector 303 then supplies thecomparator 305 with the fixed count value B as the division value DV.

The counter 304 counts the number of the clock pulses of a master clocksignal CLK which is illustrated in FIG. 7F. The counter 304 thensupplies the comparator 305 with a count value CU which indicates thecounted number. The master clock signal CLK may be the one generated inthe oscillation circuit (not shown) provided in the receiving apparatus100, or may be the one supplied from the outside of the receivingapparatus 100. The counter 304 once initialize the count value to zeroat a timing synchronized with the master clock signal CLK when a clockgate signal CG which is kept at logic level 1 is supplied. The counter304 then continues to count the number of the clock pulses of the masterclock signal CLK.

The comparator 305 compares the count value CU which increases with thepassage of time and the division value DV which indicates the abovefixed count values A and B as illustrated in FIG. 7E. The comparator 305supplies a reset terminal of the counter 304 and the AND gate 306 withthe clock gate signal CG which is kept at logic level 0 when the countvalue CU and the division value DV are different from each other, and atlogic level 1 when the count value CU matches the division value.

The AND gate 306 generates the passband setting signal TS of a clocksignal form which is illustrated in FIG. 7F by outputting the masterclock signal CLK during a period in which the clock gate signal CG is atlogic level 1. The AND gate 306 then supplies clock terminals of each ofthe Flip Flops FF1˜FFn with the passband setting signal TS.

It is described below, with reference to FIGS. 7A-7H, operations of theLPF 15 and the passband setting part 30 to which configurationsillustrated in FIG. 5 and FIG. 6 are adopted.

The comparator 305 illustrated in FIG. 6 compares the division value DVwhich indicates the fixed count value A for setting a high frequencyclock and the count value CU of the number of pulses of the master clocksignal CLK, when the synchronization detection signal CY is at logiclevel 0 as illustrated in FIG. 7C, i.e. when the synchronization signalis not yet detected. The comparator 305 generates the clock gate signalCG which is at logic level 1 when the division value DV matches thecount value CU. The count value of the counter 304 is initialized tozero in response to the clock gate signal CG at logic level 1. One pulseof the clock signal in the master clock signal CLK is generated as thepassband setting signal TS from the AND gate 306.

The passband setting part 30 generates the passband setting signal TS inthe form of a clock signal having frequency corresponding to the fixedcount value A during a period in which the synchronization detectionsignal CY is kept at logic level 0. The passband setting part 30 thensupplies the clock terminal of each of the flip flop FF1˜FFn of the LPF15 with the passband setting signal TS.

The comparator 305 compares the division value DV which indicates thefixed count value B for setting low frequency clock and the count valueCU, when the synchronization signal is detected and the synchronizationsignal CY makes transition from logic level 0 to level 1 as illustratedin FIG. 7C. The comparator 305 generates the clock gate signal which isat logic level 1 when the division value DV matches the count value CV.The count value of the counter 304 is initialized to zero in response tothe clock gate signal CG which is at logic level 1. One pulse of theclock signal in the master clock signal CLK is generated as the passbandsetting signal TS from the AND gate 306.

The passband setting part 30 generates the passband setting signal TS inthe form of the clock signal having frequency corresponding to the fixedcount value B during a period in which the synchronization detectionsignal CY is kept at logic level 1. The passband setting part 30 thensupplies the clock terminal of each of the flip flop FF1˜FFn of the LPF15 with the passband setting signal TS.

The fixed count value A is smaller than the fixed count value B. Whenthe division value DV indicates the fixed count value A, the count valueof the pulses of the master clock signal CLK reaches the division valueDV in a shorter period than in the case the division value DV indicatesthe fixed count value B.

The frequency of the clock signals in the passband setting signal TSbecomes higher in a period in which the fixed count value A is set asthe division value DV than in a period in which the fixed count value Bis set as the division value DV. In the LPF having the configuration ofthe digital-type transversal filter as illustrated in FIG. 5, the higherthe frequency of the signal which is supplied to the clock terminal ofeach of the flip flops FF1˜FFn becomes, the broader the bandwidth of thepassband becomes.

Therefore, it is possible to broaden the passband width of the LPF 15during a period in which the synchronization detection signal CY is keptat logic level 0 and to narrow the passband width of the LPF 15 during aperiod in which the synchronization detection signal CY is kept at logiclevel 1, when the configurations which is illustrated in FIG. 5 and FIG.6 are adopted to the LPF15 and the passband setting part 30.

In the configuration which is illustrated in FIG. 5 and FIG. 6, thepassband setting part 30 controls the passband width of the LPF 15 bychanging frequency of the passband setting signal TS as a clock signal.However, the passband setting part 30 may control the passband width ofthe LPF 15 by changing the filter coefficient C1˜Cn which is illustratedin FIG. 5. The passband setting part 30 stores in advance the filtercoefficient C1˜Cn for obtaining the frequency characteristic L1 which isillustrated in FIG. 2 and the filter coefficient C1˜Cn for obtaining thefrequency characteristic L2 which is broader than the frequencycharacteristic L1. The passband setting part 30 supplies each of thecoefficient multipliers M1˜Mn in the LPF 15 with the passband settingsignal TS which indicates the filter coefficient C1˜Cn for obtaining thefrequency characteristic L2 during a period in which the synchronizationdetection signal CY is kept at logic level 0 as illustrated in FIG. 3C.The passband setting part 30 supplies each of the coefficientmultipliers M1˜Mn in the LPF 15 with the passband setting signal TSwhich indicates the filter coefficient C1˜Cn for obtaining the frequencycharacteristic L1 which is narrower than the frequency characteristicL1, i.e. the upper limit of frequency of which is lower than that of thefrequency characteristic L2, during a period in which thesynchronization detection signal CY is kept at logic level 1.

The receiving apparatus 100 which is illustrated in FIG. 1 receiveswireless transmission waves modulated in digital in FSK scheme as thereception target. However, the modulation scheme for receiving thewireless transmission waves is not limited to the FSK scheme. Thereceiving apparatus 100 which is illustrated in FIG. 1 may receive thewireless transmission waves modulated in digital modulation schemeincluding not only FSK but also ASK(amplitude shift keying), PSK(phasesift keying), QAK(quadrature amplitude modulation) and so on.

In the above example, the synchronization detector 21 generates thesynchronization detection signal CY which is kept at logic level 0during a period in which the synchronization signal is not detected andwhich is kept at logic level 1 after the synchronization signal isdetected. However, the synchronization detector 21 may generate thesynchronization detection signal CY which is kept at logic level 1during a period in which the synchronization signal is not detected andwhich is kept at logic level 0 after the synchronization signal isdetected.

In other words, receiving apparatus 100 may be for demodulating areceived signal obtained by receiving a wireless transmission wave whichis modulated according to a series of data sequences including frameseach having a synchronization signal, comprising: frequency convertingparts (12˜14), a filter (15), a frequency detector (16), a frequencyoffset detector (17), a frequency correction part (22), asynchronization detector (21) and a passband setting part (30). Thefrequency converting part performs a frequency conversion on thereceived signal (AR) and obtains a frequency converted signal includinga baseband signal (BDI, BDQ). The filter eliminates high frequency noisecomponents from the frequency converted signal and obtains a highfrequency noise eliminated signal (BNI, BNQ). The frequency detectorperforms a frequency detection on the high frequency noise eliminatedsignal and obtains a frequency detection signal (FD). The frequencyoffset detector detects a frequency offset (OC) occurring in thefrequency converted signal on the basis of the frequency detectionsignal. The frequency correction part sifts frequency of the frequencyconverted signal by the amount of the frequency offset. Thesynchronization detector detects the presence of the synchronizationsignal for each frame and generates a synchronization detection signal(CY) which has a first level as far as the synchronization signal is notdetected and has a second level when and after the synchronizationsignal is detected. The passband setting part sets an upper limit offrequency of a passband in the filter at a lower frequency within aperiod in which the synchronization detection signal is kept at thesecond level than that within a period in which the synchronizationdetection signal is kept at the first level.

It is understood that the foregoing description and accompanyingdrawings set forth the preferred embodiments of the present invention atthe present time. Various modifications, additions and alternativedesigns will, of course, become apparent to those skilled in the art inlight of the foregoing teachings without departing from the spirit andscope of the disclosed invention. Thus, it should be appreciated thatthe present invention is not limited to the disclosed Examples but maybe practiced within the full scope of the appended claims.

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2015-015316 filed on Jan. 29,2015, the entire contents of which are incorporated herein by reference.

What is claimed is:
 1. A receiving apparatus for demodulating a receivedsignal obtained by receiving a wireless transmission wave which ismodulated according to a series of data sequences including frames eachhaving a synchronization signal, the receiving apparatus comprising: afrequency converting part for performing a frequency conversion on thereceived signal and obtaining a frequency converted signal including abaseband signal, a filter for eliminating high frequency noisecomponents from the frequency converted signal and obtaining a highfrequency noise eliminated signal, a frequency detector for performing afrequency detection on the high frequency noise eliminated signal andobtaining a frequency detection signal, a frequency offset detector fordetecting a frequency offset occurring in the frequency converted signalon the basis of the frequency detection signal, a frequency correctionpart for sifting frequency of the frequency converted signal by theamount of the frequency offset, a synchronization detector for detectingthe presence of the synchronization signal in each of said frames, andgenerating a synchronization detection signal which has a first level asfar as the synchronization signal is not detected and has a second levelwhen and after the synchronization signal is detected; and a passbandsetting part for setting an upper limit of frequency of a passband inthe filter at a lower frequency within a time period in which thesynchronization detection signal is kept at the second level than thatwithin a time period in which the synchronization detection signal iskept at the first level.
 2. The receiving apparatus according to claim1, wherein said filter is a transversal filter including 1st to nth(where the n denotes an integer of 2 or more) flip flops connected incascade, 1st to nth coefficient multipliers for multiplying outputs fromthe 1st to nth flip flops by 1st to nth filter coefficients, an adderfor outputting the addition result obtained by adding the multiplicationresults of each of the coefficient multipliers as the high frequencynoise eliminated signal, wherein said passband setting part supplieseach of the 1st to nth flip flops with a low frequency clock signal whenthe synchronization signal makes transition from the first level to thesecond level in each of said frames.
 3. The receiving apparatusaccording to claim 1, wherein said filter is a low pass filter includinga transversal filter, wherein said passband setting part changes filtercoefficients in said transversal filter when the synchronization signalmakes transition from the first level to the second level in each ofsaid frames.
 4. A receiving method for a receiving apparatus comprisinga frequency converting part for performing a frequency conversion on thereceived signal and obtaining a frequency converted signal including abaseband signal, a filter for eliminating high frequency noisecomponents from the frequency converted signal and obtaining a highfrequency noise eliminated signal, a frequency detector for performing afrequency detection on the high frequency noise eliminated signal andobtaining a frequency detection signal, and a frequency offset detectorfor detecting a frequency offset occurring in the frequency convertedsignal on the basis of the frequency detection signal, the receivingmethod comprising the steps of: detecting the presence of thesynchronization signal in each frame, and generating a synchronizationdetection signal which has a first level as far as the synchronizationsignal is not detected and has a second level when and after thesynchronization signal is detected, setting an upper limit of frequencyof a passband in the filter at lower frequency within a time period inwhich the synchronization detection signal is kept at the second levelthan that within a time period in which the synchronization detectionsignal is kept at the first level.